Brief
Immersion DUV lithography is the technique the semiconductor industry uses to print transistors and interconnects onto silicon. The core physics principle is resolution: to print smaller features, you need shorter light. An argon fluoride excimer laser generates ultraviolet light at 193 nanometers (nm) — close to the boundary of what glass optics can transmit. In dry lithography, this light passes through air before hitting the wafer, which limits the maximum achievable numerical aperture (NA) to below 1.0. Immersion lithography fills that gap with ultrapure water, which has a refractive index of 1.44 at 193nm; this effectively compresses the exposure wavelength and allows NA to reach 1.35 in production systems, pushing single-exposure resolution well below the diffraction limit for air. ASML's current top NXT machines run at NA 1.35, with overlay accuracy of 1.6–2.5nm, and throughput of 295–330 wafers per hour. Yuliangsheng's machine also targets 193nm ArF immersion at NA 1.35, designed for 28nm-class single-exposure resolution — a specification class ASML first commercialized roughly in the 2008–2012 timeframe with its NXT:1950i.
The machine operates as a step-and-scan system. The wafer sits on a precision stage that moves in incremental steps across the 300mm silicon surface; at each position, the scanner exposes a small "field" (typically a rectangle corresponding to one or a few die) through a photomask containing the circuit pattern for that layer. This is not a single-shot exposure of the whole wafer — the stage scans the wafer field by field, requiring atomic-scale positional accuracy at scanning speeds of hundreds of millimeters per second. After exposure, the photoresist chemically reacts to the UV dose, then the wafer exits the scanner for chemical development and etching steps that physically remove or retain material in the patterned areas. A modern chip requires hundreds of such lithography-etch cycles, each building one more layer of the three-dimensional transistor structure. The lithography tool controls only the exposure step — but it is the rate-limiting, precision-critical bottleneck because every subsequent layer must align to the one below it within a fraction of a nanometer, a property called overlay.
To get below 28nm without EUV, the Yuliangsheng tool (like its ASML predecessors) relies on multi-patterning: a single layer of the chip is broken into two or more sub-patterns, each requiring a separate lithography pass and etch cycle, with the combined result producing features finer than a single exposure could resolve. Self-aligned quadruple patterning (SAQP), for example, uses one exposure to define a template, then grows and etches spacer films around it to generate four times as many lines. This technique is how SMIC currently produces its most advanced logic nodes using ASML's older DUV tools — and it is the same pathway Yuliangsheng's machine would theoretically enable if its overlay performance is tight enough. Reliable multi-patterning at 7nm requires overlay errors below roughly 2nm across the full wafer; whether the Yuliangsheng tool can hold that spec in production conditions is unknown as of July 2026 — SMIC has been testing it since September 2025 but has not confirmed production-line insertion.
Yuliangsheng is a startup subsidiary of Si Carrier of Shenzhen, staffed heavily with former Huawei engineers. Its machine is built predominantly from Chinese-sourced components, with some critical parts still imported from Japan. The supply-chain residual dependency on Japan is the tool's most exposed vulnerability: if Japan follows the US and Netherlands in restricting component exports, the tool's producibility is at risk. The broader domestic DUV effort includes a parallel competitor, SMEE, which has reportedly sold roughly ten units of its SSA800 series targeting the same 28nm immersion node. The two programs together are producing at trace volumes: Yuliangsheng targets roughly five systems in 2026 and twenty in 2027, against the 131 immersion DUV systems ASML shipped in 2025.
The geopolitical forcing function is direct. EUV machines — which print features below 7nm in single exposure — have been completely blocked from China for years. With DUV import restrictions tightening (the proposed US MATCH Act in April 2026 would extend controls explicitly to immersion DUV), China's domestic fabs face a ceiling. The Yuliangsheng machine, if it meets production-line specs, does not eliminate that ceiling — chips requiring EUV still cannot be made. But it seals the 28nm floor: SMIC, Hua Hong, and CXMT can continue 28nm-class production and potentially extend to 7nm via multi-patterning without needing ASML replenishment. For CXMT specifically, the target is 3D DRAM — stacking memory cells vertically using DUV for horizontal patterning plus hybrid bonding — a strategy that sidesteps the node-shrink problem rather than solving it.
Components (8)
ArF Excimer Laser Source
Generates pulsed UV light at exactly 193nm by electrically exciting argon fluoride gas; pulse frequency and power stability directly determine exposure dose uniformity across the wafer. The laser must sustain output at approximately 6 kHz to support production throughput.
Illuminator and Beam-Shaping Optics
Conditions the laser beam into the precise angular distribution (pupil fill) required to illuminate the reticle uniformly. The illuminator also enables advanced modes — dipole, annular, or freeform — that optimize resolution for specific pattern geometries.
Reticle (Photomask) Stage
Holds and scans the chrome-on-quartz mask containing the circuit pattern at 4x magnification relative to the wafer target. The reticle stage must move synchronously with the wafer stage during each scan, with their relative motion controlled to nanometer precision.
Projection Lens (Catadioptric Objective)
A complex multi-element optical assembly that demagnifies the reticle pattern 4x onto the wafer while maintaining diffraction-limited image quality across the full exposure field. In immersion systems, the final element of this lens is submerged in water. The lens is the single hardest-to-manufacture component — requiring sub-nanometer surface figure accuracy and controlled thermal expansion — and the primary differentiator between early-generation and leading-edge tools.
Immersion Hood and Water Management System
Confines a thin film of ultrapure water in the gap between the lens and the moving wafer surface, forming a stable meniscus that travels with the stage. The hood must prevent bubbles, maintain temperature uniformity, and avoid contaminating either the lens or the photoresist. Any bubble or water droplet left on the wafer is a defect.
Dual Wafer Stage System
Modern immersion scanners use two independent stages on the same platform: one stage exposes under the lens while the other simultaneously loads a new wafer and performs alignment measurements. ASML's production NXT systems derive a significant fraction of their throughput advantage from this dual-stage architecture, which keeps the laser firing continuously. Whether Yuliangsheng's first tool uses a dual-stage design has not been confirmed in available sources.
Alignment and Overlay Metrology System
Reads alignment marks printed in prior layers to compute the precise position and rotation of the wafer before each exposure. Overlay error — the offset between a newly printed pattern and the layer beneath it — is the fundamental limit on multi-patterning feasibility. ASML's NXT:1980Di achieves matched-machine overlay below 2.5nm; a 28nm tool pushed toward 7nm via multi-patterning needs overlay tightly controlled at that level or better.
Computational Lithography Software (SMO/OPC)
Pre-corrects the reticle pattern for known optical distortions so the printed feature on the wafer matches the intended design. Optical proximity correction (OPC) modifies mask geometries to counteract edge diffraction effects; source-mask optimization (SMO) co-optimizes the illuminator shape and mask pattern together. This software layer is as critical as the hardware — without it, features at advanced nodes print incorrectly regardless of lens quality.
How It Works (8 steps)
1Wafer coating: photoresist applied to silicon surface
A bare silicon wafer is spin-coated with a photoresist — a polymer film that chemically changes when exposed to 193nm light. The coating must be uniform to nanometer-scale thickness across the 300mm diameter. An anti-reflective coating is typically applied beneath the resist to prevent standing-wave interference from back-reflected UV.
Wafer track tool (separate from the scanner)Photoresist and coating chemistry supplier
Why this step: The photoresist is the recording medium — without it, the UV exposure leaves no physical record. Coating uniformity sets the baseline for line-width control across the wafer.
2Wafer loading and alignment to prior layers
The coated wafer is loaded onto the scanner stage. The alignment system locates dedicated alignment marks printed in earlier process layers and computes corrections for wafer position, rotation, and magnification. For the first layer on a blank wafer, the stage uses factory-calibrated coordinates; for every subsequent layer, it must register to the existing pattern within the overlay budget.
Wafer handler robotAlignment sensor systemStage interferometers
Why this step: Every layer of a multi-layer chip must land precisely on top of the previous one. A misregistered layer renders the entire chip defective; in multi-patterning flows, two passes of the same tool must align to each other within a fraction of the target feature pitch.
3Immersion water fill: meniscus established under lens
Before scanning begins, the immersion hood delivers ultrapure water into the gap between the final lens element and the wafer surface, forming a stable liquid meniscus. Water at 193nm has a refractive index of 1.44, which effectively increases the system's numerical aperture beyond what air allows — enabling finer resolution without changing the laser wavelength. The water must be kept bubble-free, temperature-stable, and free of particles.
Immersion hood moduleUltrapure water delivery and recirculation system
Why this step: The immersion medium is what enables sub-40nm resolution from a 193nm laser. Without the water gap, numerical aperture is capped below 1.0 and 28nm single-exposure is physically impossible at this wavelength.
4Step-and-scan exposure: reticle pattern printed field by field
The reticle stage and wafer stage move synchronously in opposite directions at high speed — the scanner sweeps the beam across the reticle while the wafer stage moves in the perpendicular axis, printing one exposure field (die or group of dies) at a time. The pattern on the reticle is demagnified 4x through the projection lens and projected into the photoresist. After each field exposure, the wafer steps to the next position and the scan repeats. A full 300mm wafer contains hundreds of fields and takes seconds to minutes to expose completely.
ArF laserProjection lensReticle stageWafer stageImmersion hood traveling with the stage
Why this step: The step-and-scan architecture allows a small, high-quality lens to serve the entire wafer by moving rather than requiring a lens as wide as the wafer itself — smaller optics can be manufactured to higher precision, enabling the nm-level feature fidelity the process requires.
5Post-exposure bake and resist development
After exposure, the wafer undergoes a precisely timed bake on a hot plate, which drives a photochemical amplification reaction in the resist — the UV-generated acid catalyzes polymer de-protection across the exposed area, producing a sharp chemical contrast between exposed and unexposed regions. A developer solvent then dissolves the exposed resist (in positive-tone processes), leaving a three-dimensional relief pattern that physically maps the circuit geometry to be etched.
Wafer track toolDeveloper chemistry
Why this step: The resist cannot be directly etched while still uniform — development creates the physical template that subsequent etch processes use to remove or protect underlying material. The bake step is critical for line-edge roughness: incomplete amplification produces ragged pattern edges that degrade transistor performance.
6Etch and strip: circuit geometry transferred to wafer material
The patterned resist acts as a mask for dry plasma etching or wet chemical etching, which removes material from the exposed silicon, oxide, or metal layer beneath. Once the etch is complete, the remaining resist is stripped away. This step physically instantiates one layer of the circuit.
Etch tool (separate equipment)Strip chemistry
Why this step: Lithography alone creates a chemical pattern in resist, not a physical circuit feature. The etch step is what converts the optical image into durable semiconductor geometry.
7Multi-patterning repetition for sub-28nm features
To print features finer than a single 28nm-tool exposure can resolve, the same layer is divided into multiple sub-patterns, each receiving its own lithography-etch sequence. In self-aligned quadruple patterning (SAQP), a single exposure defines a spacer template; conformal deposition and selective etching then multiply the line density fourfold without a second exposure. In litho-etch-litho-etch (LELE), two separate scanner passes expose interleaved sub-patterns that together form the full target pattern. Each additional pass multiplies the overlay budget challenge: errors compound across passes.
Scanner (multiple passes)Deposition tools (ALD/CVD)Etch tools
Why this step: Multi-patterning is the mechanism that extends a 28nm-class tool toward 7nm — and also the mechanism that makes any overlay deficiency in the Yuliangsheng tool catastrophic at advanced nodes, because registration errors are unforgiving when two exposures must land within 2nm of each other.
8Inline metrology and feedback: scanner calibration updated
After each layer (or group of layers), a dedicated metrology tool measures overlay, critical dimension (CD) uniformity, and focus accuracy across the wafer. These measurements feed back into the scanner's correction models — adjusting stage positioning maps, lens heating corrections, and illumination settings — to keep subsequent exposures within spec. This closed-loop calibration system is a major source of ASML's production-line performance advantage, built from decades of matched-machine data across its global installed base.
CD-SEM and overlay metrology toolsScanner process control software
Why this step: A lithography tool drifts over time and with thermal load; without constant feedback correction, overlay and CD errors accumulate until yield collapses. A new tool like Yuliangsheng's will lack the calibration history and matched-fleet correction infrastructure that ASML tools carry from years of high-volume production.
What Makes It Work
Water as optical amplifier: immersion increases NA beyond the air limit
Filling the lens-to-wafer gap with water (refractive index 1.44) allows the projection lens to operate at NA 1.35 instead of the ~0.93 ceiling of dry systems at 193nm. Higher NA directly improves resolution by the formula R = k1 × λ / NA — so the same 193nm laser that prints 65nm features in air can print 38nm features in water at the same k1 factor. This is not a software trick; it is a fundamental optical physics change that requires a lens system designed to operate submerged, with all the contamination-control complexity that entails.
Multi-patterning as a node extender — and its compounding alignment tax
By splitting one target pattern into two or more sequential exposures, multi-patterning can print features at half or quarter pitch relative to the single-exposure limit — allowing a 28nm-class tool to produce structures at 7nm pitch. The tax is cycle time (more passes per layer) and overlay accuracy (each additional pass must land within a shrinking error budget on top of the last). The Yuliangsheng tool's practical ceiling at advanced nodes will be determined almost entirely by its production-condition overlay accuracy, which has not been independently verified.
Overlay as the binding constraint — not wavelength
At 28nm single exposure, the physics of the water-immersion system is sufficient; the challenge of pushing to 7nm via multi-patterning is not optics but mechanical precision. The wafer stage must return to within roughly 2nm of the same position on a second pass hours later, after thermal cycling, vibration, and stage wear. ASML's machines achieve this through decades of calibration refinement, sensor development (the PARIS aberration sensor, ORION alignment system), and fleet-wide data — none of which Yuliangsheng inherits. A tool that prints 28nm cleanly in single exposure may still fail to deliver functional 7nm circuits via multi-patterning if its overlay drifts.
Throughput as a commercial and military-relevant multiplier
ASML's current NXT line achieves 295–330 wafers per hour per tool; its best machines run above 6,000 wafers per day. The Yuliangsheng tool's throughput is undisclosed, but first-generation immersion scanners historically operate at materially lower wafer-per-hour rates than mature competitors. At five units in 2026 and twenty in 2027, even at full utilization, the Yuliangsheng fleet produces a small fraction of ASML's global immersion DUV output — making this a supply-chain resilience play for China, not yet a volume production substitute.
Where It Breaks (5)
Overlay drift renders multi-patterning non-functional at advanced nodes
Consequence: If the Yuliangsheng tool cannot hold overlay below ~2nm across the full wafer in production conditions, attempts to print 7nm-class features via multi-patterning will produce unacceptable defect rates and yield loss — restricting the tool to its 28nm single-exposure envelope regardless of the theoretical claim.
Safeguard: Inline overlay metrology with feedback correction can partially compensate, but the hardware baseline (stage precision, thermal management, vibration isolation) sets a floor that software cannot fully overcome.
Residual Japanese component dependency breaks the supply chain
Consequence: The tool currently relies on some critical components from Japan. If Japan aligns with US and Dutch export controls on immersion DUV components — a plausible scenario given the trajectory of the MATCH Act discussions in April 2026 — Yuliangsheng's production ramp could be halted at the part level before it scales.
Safeguard: Yuliangsheng is actively working to localize the full supply chain, but the timeline for replacing Japanese precision optics and motion-control components with domestic equivalents is not publicly known.
Throughput and uptime gap prevents economic production-line insertion
Consequence: Even if the tool meets overlay spec, a low wafers-per-hour rate means a fab would need disproportionately more Yuliangsheng scanners than ASML scanners to achieve the same output — inflating cost per wafer and potentially making the domestic tool commercially nonviable for volume customers like SMIC.
Safeguard: None in the near term; throughput is a function of stage velocity, laser power, and dual-stage architecture — all requiring iterative hardware generations to improve.
Lens quality insufficient for sub-28nm imaging fidelity
Consequence: The projection lens is the hardest component to manufacture — it requires sub-nanometer surface figure accuracy across complex multi-element assemblies. A first-generation domestically produced lens that falls short of this spec will produce line-edge roughness and CD variation that degrades transistor performance, effectively capping the manufacturable node above the tool's theoretical resolution.
Safeguard: ASML relies on Carl Zeiss (Germany) for its projection optics — a supply relationship built over decades. China does not have an equivalent domestic precision optics supplier at this specification level as of available reporting; this is one of the three barriers identified in The Diplomat's July 2026 analysis of Chinese EUV progress.
Qualification timeline slippage at SMIC delays production insertion
Consequence: A scanner testing at first-light is years from production-line qualification. SMIC began testing the Yuliangsheng tool in September 2025; 'as early as 2027' for production insertion is an aspirational milestone, not a confirmed schedule. If qualification surfaces fundamental issues — overlay, defectivity, uptime — production insertion slips, and the tool's strategic value is deferred.
Safeguard: Parallel development at SMEE (SSA800 series, reportedly ~10 units sold) provides a fallback at the same 28nm node class.
Why It's Built This Way
Immersion DUV is designed to extract maximum resolution from a fixed wavelength (193nm) by substituting a higher-refractive-index medium for air — a straightforward optical physics approach that requires extreme mechanical and chemical engineering to implement. The fundamental tradeoff is complexity for reach: adding water dramatically increases the precision requirements for stage control, contamination management, and lens design, but avoids the far greater complexity of generating, controlling, and exposing with shorter wavelengths (EUV at 13.5nm requires a vacuum environment, reflective optics, and a plasma-based light source that took ASML 30 years to commercialize). The Yuliangsheng machine optimizes for national supply-chain independence at proven node classes rather than frontier capability — accepting a 15-year technology lag relative to ASML's current NXT line in exchange for a domestically producible tool that secures China's existing 28nm production floor against further export restrictions.
Facts & Figures (6)
The claims behind this analysis, each with its verification status — including what is contested, unverified, or could not be established.
Water has a refractive index of 1.44 at 193nm, enabling NA above 1.0 and single-exposure resolution well below the 193nm wavelength in immersion lithography.
This is the entire physical basis for immersion DUV — without it, 193nm dry lithography cannot reach 28nm features, making the water-gap the irreducible core of the machine.
✓ VERIFIEDsource ↗Result [3] directly confirms that ArF immersion lithography uses a high-refractive-index liquid with n ≈ 1.44 to achieve numerical aperture beyond 1.0, enabling resolution below the 193nm wavelength. Shanghai Yuliangsheng Technology began limited production of 193nm ArF immersion DUV machines targeting 28nm-class processes in July 2026, with initial deliveries planned to SMIC, Hua Hong, and CXMT.
Confirms the transition from prototype/test phase to limited production — the threshold that triggered ASML's stock decline and US legislative attention.
✓ GROUNDED
ASML's TWINSCAN NXT:1980Fi achieves 38nm resolution, 2.5nm machine-matched overlay, and 330 wafers per hour; its current top immersion DUV line runs over 6,000 wafers per day.
Sets the quantified benchmark against which Yuliangsheng's unverified throughput and overlay specs must be measured — the gap is the product's key unknown.
✓ GROUNDED
Yuliangsheng's tool is described as comparable to ASML's NXT:1950i from approximately 2008, which targeted 32nm-class single-exposure resolution.
Anchors the approximately 15–18-year technology lag between Yuliangsheng's first production machine and ASML's current shipping product.
✓ GROUNDED
ASML shipped 131 immersion DUV systems in 2025; Yuliangsheng targets five units in 2026 and twenty in 2027.
Quantifies the volume gap — at 20 units per year, Yuliangsheng produces roughly 15% of ASML's annual immersion DUV output, before accounting for per-machine performance differences.
✓ GROUNDED
China accounted for 33% of ASML's 2025 revenue; ASML generated €32.7 billion total in 2025, with DUV systems contributing €12 billion of that.
Quantifies what is at stake for ASML commercially, and why the domestic Chinese alternative — even at small volumes — directly threatens ASML's largest single national market.
✓ GROUNDED